A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients

When a high energy particle strikes an integrated circuit, the electron-hole pairs generated in the substrate get collected at source/drain regions. The net effect on the circuit is a transient current (single event transient or SET) injected into circuit nodes. This SET can propagate and cause an error in a state register, which is called a single-event upset (SEU). We perform a detailed characterization of the impact of an SET on a logic circuit. We observe that the impact of an SET can be understood only as a two cycle phenomenon, with several possible SEU outcomes. To understand the relative probabilities of these outcomes, we perform a detailed characterization of the impact of an SET using a Monte Carlo sampling scheme which uses post-layout circuit simulations. These simulations were run in 180nm and 65nm technologies with circuits from ISCAS'85 and ITC'99 benchmarks as test cases. Based on these simulations, we observe that all the SEU outcomes are represented to a substantial extent. Further, there is a substantial fraction of outcomes in which the SET affects multiple state registers. This indicates that the traditional view of impact of an SET on a circuit as a single bit-flip and a single cycle phenomenon may not be fully justified. The impact of an SET is in reality, distributed across two cycles and across multiple state register bits.